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UTRON
Rev. 1.1 FEATURES
Access time : 35/70ns (max.) Low power consumption : Operating : 45/30 mA (typ.) CMOS Standby : 2mA (typ.) normal 2 A (typ.) L-version 1 A (typ.) LL-version Single 4.5V~5.5V power supply Operating temperature : Commercial : 0~70 All inputs and outputs TTL compatible Fully static operation Three state outputs Data retention voltage : 2V (min.) Package : 28-pin 600 mil PDIP 28-pin 330 mil SOP
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
The UT6264C is a 65,536-bit low power CMOS static random access memory organized as 8,192 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. Easy memory expansion is provided by using two chip enable input.( CE 1 ,CE2) ,and supports low data retention voltage for battery back-up operation with low data retention current. The UT6264C operates from a single 4.5V~5.5V power supply and all inputs and outputs are fully TTL compatible.
PIN CONFIGURATION
NC A12 A7 1 2 3 4 28 27 26 25 Vcc
WE
FUNCTIONAL BLOCK DIAGRAM
A0-A12 DECODER 8K x 8 MEMORY ARRAY
CE2 A8 A9 A11
OE
A6 A5 A4
UT6264C
5 6 7 8 9 10 11 12 13 14
24 23 22 21 20 19 18 17 16 15
Vcc Vss
A3 A2 A1
A10
CE1
I/O1-I/O8
I/O DATA CIRCUIT
COLUMN I/O
A0 I/O1 I/O2 I/O3 Vss
I/O8 I/O7 I/O6 I/O5 I/O4
CE1 CE2
OE WE
CONTROL CIRCUIT
PDIP/SOP
PIN DESCRIPTION
SYMBOL A0 - A12 I/O1 - I/O8 CE1 ,CE2 WE OE VCC VSS NC DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Inputs Write Enable Input Output Enable Input Power Supply Ground No connection
GENERAL DESCRIPTION
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P80028
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UTRON
Rev. 1.1 ABSOLUTE MAXIMUM RATINGS*
PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Commercial Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to +7.0 0 to +70 -65 to +150 1 50 260
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
UNIT V W mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE Standby Standby Output Disable Read Write
CE1 H X L L L
CE2 X L H H H
OE X X H L X
WE X X H H L
I/O OPERATION High - Z High - Z High - Z DOUT DIN
SUPPLY CURRENT ISB, ISB1 ISB, ISB1 Icc,Icc1,Icc2 Icc,Icc1,Icc2 Icc,Icc1,Icc2
note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS (VCC = 4.5V~5.5V, TA = 0 to 70)
PARAMETER Power Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage SYMBOL TEST CONDITION Vcc VIH VIL ILI VSS VIN VCC ILO VOH VOL ICC Operating Power Supply Current Icc1 VSS VI/OVCC; CE1 =VIH;or CE2=VIL; or OE = VIH ;or WE = VIL IOH = - 1mA IOL = 4mA - 35 Cycle time=Min,II/O = 0mA; - 70 CE1 = VIL , CE2= VIH Cycle time=1us; II/O = 0mA ; CE1 =0.2V; CE2=Vcc-0.2V; other pins at 0.2V or Vcc-0.2V Cycle time=500ns;II/O = 0mA; CE1 =0.2V; CE2=Vcc-0.2V; other pins at 0.2V or Vcc-0.2V Normal CE1 = VIH or CE2= VIL - L/- LL Normal CE1 VCC-0.2V ; -L or CE2 0.2V; - LL other pins at 0.2V or Vcc-0.2V MIN. TYP. MAX. UNIT 4.5 5.0 5.5 V 2.2 VCC+0.5 V - 0.5 0.8 V -1 1 A -1 2.4 45 30 20 1 0.4 60 45 30 A V V mA mA mA
Icc2 Standby Current (TTL) Standby Current (CMOS) ISB ISB1
-
10 1 0.3 2 2 1
15 10 3 5 100 50
mA mA mA mA A A
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
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UTRON
Rev. 1.1 CAPACITANCE (TA=25, f=1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
-
MAX 8 10
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 100pF, IOH/IOL = -1mA/4mA
AC ELECTRICAL CHARACTERISTICS (VCC = 4.5V~5.5V, TA = 0 to 70)
(1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write-Time Output Active from End of Write Write to Output in High-Z SYMBOL UT6264C-35
MIN. MAX.
SYMBOL
UT6264C-35
MIN. MAX.
UT6264C-70
MIN. MAX.
UNIT
tRC tAA tACE1, tACE2 tOE tCLZ1*, tCLZ2* tOLZ* tCHZ1*, tCHZ2* tOHZ* tOH
35 10 5 5
35 35 25 25 25 -
70 10 5 5
70 70 35 35 35 -
ns ns ns ns ns ns ns ns ns
UT6264C-70
MIN. MAX.
UNIT
tWC tAW tCW1, tCW2 tAS tWP tWR tDW tDH tOW* tWHZ*
35 30 30 0 25 0 20 0 5 -
15
70 60 60 0 50 0 30 0 5 -
25
ns ns ns ns ns ns ns ns ns ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
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UTRON
Rev. 1.1 TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2,4)
tRC
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Address
tAA tOH tOH
DOUT
Data Valid
READ CYCLE 2 ( CE1 , CE2 and OE Controlled) (1,3,5,6)
t RC
Address
CE1
t AA t ACE1
CE2
t ACE2
OE
t CLZ1 t CLZ2
Dout HIGH-Z
t OE t OLZ t OH
Data Valid
t OHZ
t CHZ1 t CHZ2
HIGH-Z
Notes : 1. WE is HIGH for a read cycle. 2. Device is continuously selected OE , CE 1 =VIL and CE2=VIH. 3. Address must be valid prior to or coincident with CE 1 4. OE is low.
low and CE2 high transition; otherwise tAA is the limiting parameter.
5. tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured 500mV from steady state. 6. At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than tOLZ.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
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UTRON
Rev. 1.1
WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6)
t Address t CE1 t CE2 t
CW1 CW2 AW WC
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
t
WE
AS
t t
WHZ
t
WP
WR
t
High-Z
OW
Dout Din
(4)
t
DW
t
Data Valid
(4)
DH
WRITE CYCLE 2 ( CE 1 and CE2 Controlled) (1,2,5)
t
Address
WC
t
CE1
AW
t
AS
t
CW1
t
WR
t
CE2
CW2
WE
t t
WHZ
WP
Dout
High-Z
t
Din
DW
t
Data Valid
DH
Notes : 1.
WE or CE 1 must be HIGH or CE2 must be LOW during all address transitions.
2. A write occurs during the overlap of a low CE 1 , a high CE2 and a low WE . 3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the I/O drivers to turn off and data to be placed on the bus. 4. During this period, I/O pins are in the output state, and input singals must not be applied. 5. If the CE 1 LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high Impedance state. 6. tOW and tWHZ are specified with CL=5pF. Transition is measured 500mV from steady state.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
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UTRON
Rev. 1.1 DATA RETENTION CHARACTERISTICS (TA = 0 to 70)
PARAMETER Vcc for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time
tRC* = Read Cycle Time
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
SYMBOL TEST CONDITION VCC-0.2V or CE2 0.2V VDR CE1 Vcc=2V -L IDR CE1 VCC-0.2V or CE2 0.2V -LL tCDR tR See Data RetentionWaveforms (below)
MIN. 2.0 0 tRC*
TYP. MAX. UNIT 5.5 V 1 50 A 0.5 20 A ns ns
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) ( CE 1 controlled)
Data Retention Mode
VCC Vcc tCDR CE1 VIH CE1 VCC-0.2V VDR 2V Vcc tR VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
Data Retention Mode
VCC Vcc tCDR CE2 0.2V CE2 VIL VIL VDR 2V Vcc tR
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
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UTRON
Rev. 1.1 PACKAGE OUTLINE DIMENSION
28 pin 600 mil PDIP Package Outline Dimension
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
UNIT
SYMBOL
A1 A2 B B1 c D E E1 e eB L S Q1
INCH(BASE) 0.010 (MIN) 0.150 0.005 0.020 (MAX) 0.055 (MAX) 0.012 (MAX) 1.430 (MAX) 0.625 (MAX) 0.52 (MAX) 0.100 (TYP) 0.6 (TYP) 0.180(MAX) 0.06 (MAX) 0.08(MAX) o 15 (MAX)
MM(REF) 0.254 (MIN) 3.810 0.127 0.508(MAX) 1.397(MAX) 0.304 (MAX) 36.322 (MAX) 15.87 (MAX) 13.208 (MAX) 2.540(TYP) 15.24 (TYP) 4.572(MAX) 1.524 (MAX) 2.032(MAX) o 15 (MAX)
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
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UTRON
Rev. 1.1
28 pin 330 mil SOP Package Outline Dimension
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
SYMBOL
UNIT
INCH(REF) 0.112(max) 0.004(MIN) 0.0980.005 0.016(TYP) 0.010(TYP) 0.7130.005 0.3310.005 0.4650.012 0.050(TYP) 0.04040.008 0.0670.008 0.047(MAX) 0.003(MAX) 0~10
MM(BASE) 2.845(max) 0.102(MIN) 2.4890.127 0.406(TYP) 0.254(TYP) 18.1100.127 8.4070.127 11.8110.305 1.270(TYP) 1.02550.203 1.7020.203 1.194(MAX) 0.076(MAX) 0~10
A A1 A2 b c D E E1 e L L1 S y
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
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UTRON
Rev. 1.1 ORDERING INFORMATION
PART NO. UT6264CPC-35 UT6264CPC-35L UT6264CPC-35LL UT6264CPC-70 UT6264CPC-70L UT6264CPC-70LL UT6264CSC-35 UT6264CSC-35L UT6264CSC-35LL UT6264CSC-70 UT6264CSC-70L UT6264CSC-70LL ACCESS TIME (ns) 35 35 35 70 70 70 35 35 35 70 70 70 STANDBY CURRENT (A) (TYP.) 2mA 2A 1A 2mA 2A 1A 2mA 2A 1A 2mA 2A 1A
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
PACKAGE 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
9
UTRON
Rev. 1.1 REVISION HISTORY
REVISION Preliminary Rev. 0.1 Rev. 1.0 Rev. 1.1 DESCRIPTION Original. The timeing waveforms add CE2 control pin. 1. Revised package outline dimension. 2. Revised waveform.
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
DATE May 3 ,2001 Jun.4,2001 Jan 15,2002
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
10

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